1. Field of the Invention
The present invention relates to a plasma display panel and a module thereof, and more particularly to a plasma display panel and a module thereof that is adaptive for reducing inductance as well as simplifying an assembly process of an integrated sustainer board.
2. Description of the Related Art
Recently, a plasma display panel (hereinafter, referred to as “PDP”) has been the center of attention as a flat panel display since it is easy to be made into a large-sized panel. The PDP generally displays a picture by controlling the gas discharge period of each pixel in accordance with digital video data. Such a PDP includes three electrodes as in FIG. 1, and is typically a AC type of PDP which is driven by AC voltage.
FIG. 1 illustrates a magnified discharge cell that constitutes an AC type PDP of prior art.
A discharge cell 30 shown in FIG. 1 includes an upper plate having a sustain electrode pair 12A, 12B, an upper dielectric layer 14 and a protective film 16 which are sequentially formed on an upper substrate 10; and a lower plate having a data electrode 20, a lower dielectric layer 22, barrier ribs 24 and a phosphorus layer 26 that are sequentially formed on a lower substrate 18.
Each of the sustain electrode pair 12A, 12B includes a transparent electrode and a metal electrode that is for compensating the high resistance of the transparent electrode. The sustain electrode pair 12A, 12B is divided into a scan electrode 12A and a sustain electrode 12B. The scan electrode 12A supplies a scan signal for address discharge and a sustain signal for sustain discharge, and the sustain electrode 12B supplies a sustain signal. The data electrode 20 is formed to cross the sustain electrode pair 12A, 12B. The data electrode 20 supplies a data signal for address discharge.
Electric charges generated by the discharge are accumulated at the upper dielectric layer 14 and the lower dielectric layer 22. The protective film 16 prevents the damage of the upper dielectric layer 14 caused by sputtering and increases the emission efficiency of secondary electrons. The dielectric layer 14, 22 and the protective film 16 enable to reduce the discharge voltage applied from the outside.
The barrier ribs 24 provide a discharge space together with the upper and lower substrates 10 and 18. And the barrier ribs 24 are formed in parallel to the data electrode 20 to prevent the ultraviolet ray generated by the gas discharge from leaking to adjacent cells. The phosphorus layer 26 is spread over the surface of the lower dielectric layer 22 and the barrier ribs 24 to generate red, green and blue visible rays. The discharge space is fully filled up with an inert gas such as He, Ne, Ar, Xe, Kr, a mixture discharge gas of the above gases or an excimer gas that can generate ultraviolet ray by discharge, for gas discharge.
The discharge cell 30 of such a structure sustains the discharge in a surface discharge by the sustain electrode pair 12A 12B after being selected as an opposite discharge by the data electrode 20 and the scan electrode 12A. Accordingly, a visible ray is emitted at the discharge cell 30 by having the phosphorus 26 emit light by the ultraviolet ray that is generated upon sustain discharge. In case of this, the discharge cell 30 controls a sustain discharge period, i.e., the number of sustain discharge, in accordance with the video data to realize the gray scale required for image display. And, the color of one pixel is realized by compounding three discharge cells where each of red, green and blue phosphorus 26 is coated.
FIG. 2 illustrates an overall electrode arrangement structure of a PDP that includes the discharge cell 30 shown in FIG. 1. In FIG. 2, the discharge cell 30 is formed at every intersection of scan electrode lines Y1 to Ym, sustain electrode lines Z1 to Zm and data electrode lines X1 to Xn.
The scan electrode lines Y1 to Ym supplies scan pulses and sustain pulses to make the discharge cells 30 scanned by lines and additionally to make discharge sustained at the discharge cells 30. The sustain electrode lines Z1 to Zm commonly supply sustain pulses to make discharge sustained at the discharge cells 30 along with the scan electrode lines Y1 to Ym. The data electrode lines X1 to Xn supply data pulses, which are synchronized with the scan pulses, by lines to make a specific discharge cells selected, wherein the selected discharge cells are to have discharge sustained in accordance with the logical value of the data pulse.
A typical method in such a PDP driving method is an Address and Display Separation ADS driving method in which the PDP is driven with one frame being divided into an address period and a display period, i.e., a sustain period. In the ADS driving method, one frame is divided into a plurality of subfields corresponding to each bit of video data, and each of the subfields is divided again into a reset period, an address period and a sustain period. In such a subfield, the reset period RPD is equal to the address period APD and the sustain period SPD is given a different weight value. Accordingly, the PDP expresses the gray scale corresponding to the video data by compounding the sustain periods during which discharge is sustained, in accordance with the video data.
FIG. 3 illustrates a general driving waveform supplied to the PDP shown in FIG. 2 in a subfield SF1 among a plurality of subfields.
As in FIG. 3, in the reset period RPD, the PDP make a writing discharge generated by use of a reset pulse RP and then wall charges are removed, thereby initializing all discharge cells 30 to an off-state where the wall charges are left over. For this, a rising ramp pulse and a falling ramp pulse as reset pulse RP are supplied to the scan electrode lines Y1 to Ym, wherein the rising ramp pulse slowly increase to a peak voltage Vr on the basis of a step voltage Vs and the falling ramp pulse slowly decreases to a ground voltage 0V. A first dark discharge is generated at all the discharge cells 30 by the rising ramp pulse. And then, a second dark discharge is generated at all the discharge cells 30 by the falling ramp pulse and a bias pulse BP supplied to the sustain electrode lines Z1 to Zm. Subsequently, the wall charges formed at the scan electrode lines Y1 to Ym and the sustain electrode lines Z1 to Zm are decreased in accordance with the falling ramp pulse, thus all the discharge cells 30 are initialized to an off-state where the wall charges are left over. In this reset period RPD, the voltage of the data electrode lines X1 to Xn is fixed at the ground voltage 0V.
In the address period APD, scan pulses SP are supplied to the scan electrode lines Y1 to Ym by lines and data pulses DP are selectively supplied to the data electrode lines X1 to Xn in synchronization with the scan pulse SP. Accordingly, an address discharge is generated at the discharge cells to which the scan pulses SP and the data pulses DP are supplied, thus they become on-state where the wall charges are sufficiently formed for the next sustain discharge. But on the other hand, no address discharge is generated at the discharge cells to which no scan pulse SP and data pulse DP is supplied, thereby remaining at the off-state.
In the sustain period SPD, Y and Z sustain pulses SUSPy, SUSPz are alternately supplied to the scan electrode lines Y1 to Ym and the sustain electrode lines Z1 to Zm to make the state of the discharge cell determined in the address period APD sustained. More specifically, the discharge cells of on-state in which the wall charges are sufficiently formed in the address period APD remain at the on-state by discharge caused by the Y and Z sustain pulses SUSPy, SUSPz, and the discharge cells of off-state remain at the off-state without discharge.
In an erasure period EPD subsequent to the sustain period SPD, erasure pulses EP are supplied to the sustain electrode lines Z1 to Zm to cause an erasure discharge, thereby eliminating the wall charges existing at all the discharge cells 30.
In order to supply such driving waveforms to the PDP shown in FIG. 2, a driving device is installed at the rear surface of a heat proof plate 64 located at the side of the rear surface of the PDP 40 as shown in FIGS. 4 and 5.
A PDP module shown in FIGS. 4 and 5 includes a Y driving board 45 to drive the scan electrode lines Y1 to Ym; a Z sustainer board 48 to drive the sustain electrode lines Z1 to Zm; a data driver board 50 to drive the data electrode lines X1 to Xm; a control board 42 to control the Y driving board 45, the Z sustainer board 48 and the data driver board 50; and a power source board (not shown) to supply power to each of the boards 42, 45, 48 and 50.
The Y driving board 45 includes a scan driver board 44 to generate reset pulses RP and scan pulses SP shown in FIG. 3, and a Y sustainer board 46 to generate the Y sustain pulses SUSPy. The scan driver board 44 supplies the scan pulse SP to the scan electrode lines Y1 to Ym of the PDP 40 through a Y conductive path 51. The Y sustainer board 46 supplies the Y sustain pulse SUSPy to the scan electrode lines Y1 to Ym through the scan driver board 44 and the Y conductive path 51.
The Z sustainer board 48 generates the bias pulse BP and the Z sustain pulse SUSz shown in FIG. 3 and supplies the generated pulse to the sustain electrode lines Z1 to Zm of PDP 40 through the Z conductive path 52.
The data driver board 50 generates the data pulse DP shown in FIG. 3 and supplies the generated pulse to the data electrode lines X1 to Xn of the PDP 40 through the X conductive path 54.
The control board 42 generates X, Y, Z timing control signals. And the control board 42 supplies the Y timing control signal to the Y driving board 45 through a first conductive path 56, the Z timing control signal to the Z sustainer board 48 through a second conductive path 58, and the X timing control signal to the data driver board 50 through a third conductive path 60.
At this moment, each conductive path is any one of a flexible flat cable or a flexible printed cable.
When driving the PDP module with such a composition, a current path in the sustain period is as follows. Firstly, when the Y sustain pulse SUSPy is supplied to the scan electrode lines Y1 to Ym in the Y driving board 45, a first current path is “Y driving board 45→scan electrode line Y1 to Ym→panel capacitor→sustain electrode line Z1 to Zm→Z sustainer board 48→heat proof plate 64→Y driving board 45”. And when the Z sustain pulse SUSPz is supplied to the sustain electrode lines Z1 to Zm in the Z sustainer board 48, a second current path is “Z sustainer board 48→sustain electrode line Z1 to Zm→panel capacitor→scan electrode line Y1 to Ym→Y driving board 45→heat proof plate 64→Z sustainer board 48”.
However, the PDP module shown in FIGS. 4 and 5 is divided into the Y sustainer board 46 and the Z sustainer board 48, which perform similar functions to each other in the same driving period to be installed, thus its power consumption increases as well as a lot of circuit parts such as switching devices are required. Accordingly, the PDP module of prior art has a problem that its composition is complicated and its manufacturing cost is high. In order to solve such a problem, a PDP module-Korea patent application laid open No. 2003-0023387-as shown in FIG. 6 has been proposed.
FIG. 6 is a diagram representing a PDP module where Y and Z sustainer boards of prior art are integrated. FIG. 7 is a diagram representing the sectional structure of the PDP module shown in FIG. 6.
The PDP module shown in FIGS. 6 and 7 includes a PDP 70; a heat proof plate 86 installed at the rear surface for the PDP 70; a Y-Z integrated board 100, a data driver board 80 and a control board 72 installed at the rear surface of the heat proof plate 86; and a power source board (not shown) that supplies power to those boards 100, 80, 72.
The PDP 70 has a structure where an upper plate 90 and a lower plate 92 are bonded to form a gas discharge space. Herein, the scan electrode lines Y1 to Ym and the sustain electrode lines Z1 to Zm are formed in parallel in the upper plate 90 as shown in FIG. 2, and the data electrode lines X1 to Xn are formed in the lower plate 92. Further, a Y pad area 94 is provided at one side of the upper plate 90 to form Y pads (not shown) connected to the scan electrode lines, and a Z pad area 96 is provided at the other side to form Z pads (not shown) connected to the sustain electrode lines (not shown). And, an X pad area (not shown) is provided at one side of the lower plate 92 to form X pads (not shown) connected to the data lines. The upper plate 90 and the lower plate 92 is bonded to have the Y pad area 94 and the Z pad area 96 and the X pad area (not shown).
The heat proof plate 86 enables the heat generated at the PDP 70 to be easily emitted to the outside. For this, the heat proof plate 86 is installed to overlap the rear surface of the PDP 70 on the whole.
The control board 72 generates X, Y, Z timing control signals. And the control board 72 supplies the Y and Z timing control signal to the Y-Z integrated board 100 through a first conductive path 76, and the X timing control signal to the data driver board 80 through a second conductive path 78.
The data driver board 80 generates data pulses DP, as shown in FIG. 3, by use of the X timing control signal from the control board 72 and supplies the generated pulse to the data electrode lines of the PDP 70 through the X conductive path 88. Herein, the X conductive path 88 is connected to the data diver board 80 and the X pad area (not shown) which is provided at PDP 70.
The Y-Z integrated board 100 includes a scan driver board 73, a Y-Z sustainer board 74 and a connector 75 to connect the two boards 73, 74 with each other.
The scan driver board 73, as shown in FIG. 3, generates reset pulses RP which are to be supplied to the scan electrode lines in the reset period APD and scan pulses SP which are to be supplied in the address period APD by use of the Y timing control signal from the control board 72. And, the scan driver board 73 supplies the reset pulse RP and the scan pulse SP to the scan electrode lines of the PDP 70 through the Y conductive path 82.
Herein, the Y conductive path 82 is connected to the scan driver board 73 and the Y pad area 94 of the PDP 70, as shown in FIG. 7.
The Y-Z sustainer board 74, as shown in FIG. 3, generates Y sustain pulses SUSPy that are to be supplied to the scan electrode lines and Z sustain pulses SUSPz that are to be supplied to the sustain electrode lines in the sustain period SPD by use of the Y and Z timing control signal from the control board 72, wherein the Y sustain pulse SUSPy or the Z sustain pulse SUSPz is alternately supplied. And, the Y-Z sustainer board 74, as shown in FIG. 3, generates bias pulses BP that are to be supplied to the sustain electrode lines in the reset period RPD and the address period APD. For this, the Y-Z sustainer board 100 includes a Y sustain circuit (not shown) to generate the Y sustain pulse SUSPy, and a Z sustain circuit (not shown) to generate the bias pulse BP and the Z sustain pulse SUSPz. The Y-Z sustainer board 74 supplies the Y sustain pulse SUSPy to the scan electrode lines of the PDP 70 through a path of “a connector 75→a scan driver board 73→the Y conductive path 82”. And the Y-Z sustainer board 74 supplies the bias pulse BP and the Z sustain pulse SUSPz to the sustain electrode lines of the PDP 70 through a Z conductive path 84.
Herein, the Z conductive path 84, as shown in FIG. 7, is connected to the Y-Z sustainer board 74 and the Z pad area 96 of the PDP 70.
In this way, the Y conductive path 82 is connected to the scan driver board 73 and the Z conductive path 84 is connected to the Y-Z sustainer board 74. Herein, the Y conductive path 82 is connected to the front surface(on the basis of PDP 70) or the rear surface of the scan driver board 73, and the Z conductive path 82 is connected to the front surface or the rear surface of the Y-Z sustainer board 74.
In case that the PDP module with such a configuration is driven, the current path is as follows in the sustain period SPD. Firstly, when the Y-Z sustainer board 74 supplies the Y sustain pulse SUSPy to the scan electrode lines of the PDP 70, a first current path is “Y-Z sustainer board 74→connector→scan driver board 73→Y conductive path 82→scan electrode line→panel capacitor→sustain electrode line→Z conductive path 84→Y-Z sustainer board 74”. And, when the Y-Z sustainer board 74 supplies the Z sustain pulse SUSPz to the sustain electrode lines of the PDP 70, a second current path is “Y-Z sustainer board 74→Z conductive path 84→sustain electrode line→panel capacitor→scan electrode line→Y conductive path 82→scan driver board 73→connector 75→Y-Z sustainer board 74”
At this moment, each conductive path is any one of a flexible flat cable or a flexible printed cable.
In such a PDP module, the Z conductive path 84 might easily give electromagnetic interference EMI to the control board 72 and the power source board (not shown) or be affected by it. Due to this, it is possible that the inductance of the Z conductive path 84 increases. Accordingly, when the Y-Z sustainer board 74 and sustain electrode lines are connected by use of that long Z conductive path 84, an electromagnetic shielding protective film should be used to reduce noise or inductance. But, there is a problem that such a protective film can be easily torn off in an assembly process.